1. Field of the Invention
The present invention relates to a Schmitt circuit implemented using insulated gate field effect transistors. More specifically, the present invention relates to such a Schmidt circuit capable of maintaining a threshold voltage with accuracy.
2. Description of the Prior Art
Conventionally, a Schmitt circuit structured as shown in FIG. 1 implemented using insulated gate field effect transistors, hereinafter referred to as MOS transistors, has been utilized in an integrated circuit such as a large scale integration.
The FIG. 1 Schmitt circuit comprises a series connection of a first, second and third MOS transistors 1', 2' and 3' connected between a voltage source VDD and the ground, and a fourth MOS transistor 4' connected between the voltage source VDD and the junction of the second and third MOS transistors 2' and 3'. The drain and the gate of the first MOS transistor 1' is connected to the voltage source VDD, so that the first MOS transistor 1' may function as a load, while the source of the first MOS transistor 1' is connected to the drain of the second MOS transistor 2' and the gate of the fourth MOS transistor and is at the same time led out as an output VOUT. An input voltage VIN is applied to the gates of the second and third MOS transistors 2' and 3'. These first, second, third and fourth MOS transistors 1', 2', 3' and 4' may be of an N-channel type and formed in the same pellet.
Now the operation of the FIG. 1 Schmitt circuit will be described with reference to FIG. 2. Referring to FIG. 2, the input voltage VIN is indicated in the abscissa and various voltages are indicated in the ordinate. Vt1, Vt2, Vt3 and Vt4 denote threshold voltages of the first, second, third and fourth MOS transistors 1', 2', 3' and 4' and a change of a back gate bias voltage of each transistor is neglected in the description for simplicity. V1 denotes the voltage at the junction of the first and second MOS transistors 1' and 2' and V2 denotes the voltage at the junction of the second and third MOS transistors 2' and 3'.
First consider a case where the input voltage VIN is zero volt. When the voltage V1 is lower than VDD-Vt1, the first MOS transistor 1' is turned on and the voltage V1 is raised to VDD-Vt1. When the voltage V2 is lower than V1-Vt4,i.e. VDD-Vt1-Vt4 in such a situation, the fourth MOS transistor 4' is turned on and the voltage V2 is raised up to VDD-Vt1-Vt4. Thus, in the case where the input voltage VIN is zero volt, the relations of V1=VDD-Vt1 and V2=VDD-Vt1-Vt4 have been established. Now consider a case where the input voltage VIN becomes higher than the threshold voltage Vt3 of the third MOS transistor 3'. Then the third MOS transistor 3' is turned on so that a current starts flowing through the fourth MOS transistor 4'. If and when the fourth MOS transistor 4' and the third MOS transistor 3' have been fabricated in the same size, then the voltage V2 starts falling at the angle of 45.degree. with respect to the abscissa. When the difference between the input voltage VIN and the voltage V2 comes to coincide with the threshold voltage Vt2 of the second MOS transistor 2', i.e. when the auxiliary line (a) representing the voltage obtained by subtracting Vt2 from the input voltage VIN intersects the line representing the voltage V2, the second MOS transistor 2' is turned on. When the second MOS transistor is turned on, the voltage V1 decreases and the impedance of the fourth MOS transistor 4' increases, whereby the voltage V2 decreases, with the result that the voltage between the gate and source of the second MOS transistor 2' is further increased. Due to the above described feed-back function, both the voltages V1 and V2 abruptly fall to the vicinity of the ground level. At the same time the fourth MOS transistor 4' is turned off.
On the other hand, in the case where the input voltage VIN falls from a sufficiently high voltage, when the difference between the input voltage VIN and the voltage V2 becomes lower than the threshold voltage Vt2 of the second MOS transistor, i.e. when the locus representing the voltage V2 intersects the auxiliary line (a), the second MOS transistor 2' is turned off and the voltage V1 returns to the initial voltage VDD-Vt1 and at the same time the fourth MOS transistor 4' is turned on again, whereby the voltage V2 returns to the locus having the angle of the 45.degree. with respect to the abscissa. When the input voltage VIN further becomes lower than the threshold voltage Vt3 of the third MOS transistor 3', the third MOS transistor 3' is turned off and the voltage V2 returns to the initial voltage VDD-Vt1-Vt4.
If and when the input voltage VIN is maintained zero volt for a long period of time in the above described circuit, the voltage V1 is placed in a floating state. Therefore, if and when the voltage V1 is changed toward the source voltage VDD due to an ordinary noise, a leakage current or the like, the voltage V1 is maintained in such increased voltage. Accordingly, the voltages V1 and V2 increase as shown by the dotted line in FIG. 2, with the result that the threshold voltage VTH is changed.
Now the threshold voltage VTH on the respective occasions will be evaluated based on FIG. 2. Since the first, second, third and fourth MOS transistors have been formed in the same chip, the threshold voltages Vt1, Vt2, Vt3 and Vt4 are equal to each other. Therefore, the threshold voltage VTH may be expressed by the following equation. ##EQU1##
On the other hand, assuming that the voltage V1 becomes higher by V.alpha. due to a noise, then the threshold voltage VTH may be expressed as follows. ##EQU2##
Accordingly, it follows that the threshold voltage VTH is shifted by (V.alpha./2) due to an influence caused by a noise or the like.